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NXP Semiconductors
PCA9633
4-bit Fm+ I 2 C-bus LED driver
10. Application design-in information
V DD = 2.5 V, 3.3 V or 5.0 V
5V
12 V
I 2 C-BUS/SMBus
MASTER
SDA
SCL
OE
10 k ?
10 k ?
10 k ? (1)
SDA
SCL
OE
V DD
LED0
LED1
LED2
LED3
PCA9633
A0
A1
A2
A3
A4
A5
A6
V SS
002aab286
I 2 C-bus address = 0010 101X.
All of the 4 LEDn outputs con?gurable as either open-drain or totem pole. Mixing of con?gurations is not possible.
(1) OE requires pull-up resistor if control signal from the master is open-drain.
Fig 22. Typical application
Question 1: What kind of edge rate control is there on the outputs?
? The typical edge rates depend on the output con?guration, supply voltage, and the
applied load. The outputs can be con?gured as either open-drain NMOS or totem pole
outputs. If the customer is using the part to directly drive LEDs, they should be using it
in an open-drain NMOS, if they are concerned about the maximum ISS and ground
bounce. The edge rate control was designed primarily to slow down the turn-on of the
output device; it turns off rather quickly (~1.5 ns). In simulation, the typical turn-on
time for the open-drain NMOS was ~14 ns (V DD = 3.6 V; C L = 50 pF; R PU = 500 ? ).
Question 2: Is ground bounce possible?
? Ground bounce is a possibility, especially if all 16 outputs are changed at full current
(25 mA each). There is a fair amount of decoupling capacitance on chip (~50 pF),
which is intended to suppress some of the ground bounce. The customer will need to
determine if additional decoupling capacitance externally placed as close as
physically possible to the device is required.
PCA9633_5
? NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 25 July 2008
26 of 43
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